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CY62136V MoBL(R)
2-Mbit (128K x 16) Static RAM
Features
* High speed -- 55 ns * Temperature Ranges -- Industrial: -40C to 85C -- Automotive: -40C to 125C * Wide voltage range -- 2.7V - 3.6V * Ultra-low active, standby power * Easy memory expansion with CE and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected * CMOS for optimum speed/power * Available in a Pb-free and non Pb-free 44-pin TSOP Type II (forward pinout) and 48-ball FBGA packages This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the Truth Table at the back of this data sheet for a complete description of read and write modes.
Functional Description[1]
The CY62136V is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current.
Logic Block Diagram
DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
128K x 16 RAM Array
SENSE AMPS
I/O0 - I/O7 I/O8 - I/O15
COLUMN DECODER
BHE WE CE OE BLE
A12
A11
A13
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05087 Rev. *D
*
198 Champion Court
A14 A15 A16
*
San Jose, CA 95134-1709 * 408-943-2600 Revised July 19, 2006
CY62136V MoBL(R)
Product Portfolio
Power Dissipation (Industrial) VCC Range (V) Product CY62136VLL Min. 2.7 Typ.
[2]
Operating, ICC (mA) Max. 3.6 Speed 55 70 Grades Industrial Industrial Automotive Typ. 7 7 7
[2]
Standby, ISB2 (A) Typ.[2] 1 1 1 Maximum 15 15 20
Maximum 20 15 20
3.0
Pin Configurations[3, 4 ]
TSOP II (Forward) Top View
A4 A3 A2 A1 A0 I/O 0 I/O 1 I/O 2 I/O 3 VCC VSS I/O 4 I/O 5 I/O 6 I/O 7 WE A 16 A 15 A 14 A 13 A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
CE
A5 A6 A7 OE BHE BLE I/O 15 I/O 14 I/O 13 I/O 12 VSS VCC I/O 11 I/O 10 I/O 9 I/O 8 NC A8 A9 A 10 A 11 NC
48-ball FBGA Top View
1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 NC 2 OE BHE I/O10 I/O11 3 A0 A3 A5 NC 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 NC I/O0 I/O2 Vccq Vssq I/O6 I/O7 NC A B C D E F G H
I/O12 DNU I/O13 NC A8 A14 A12 A9
Notes: 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ, TA = 25C. 3. NC pins are not connected on the die. 4. E3 (DNU) pin have to be left floating or tied to VSS to ensure proper operation.
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CY62136V MoBL(R)
Pin Definitions
Pin Number 1-5, 18-22, 24-27, 42-45 Type Input A0-A16. Address Inputs I/O0-I/O15. Data lines. Used as input or output lines depending on operation NC. This pin is not connected to the die Description
7-10, 13-16, 29-32, 35-38 Input/Output 23 17 6 40, 39 No Connect
Input/Control WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted Input/Control CE. When LOW, selects the chip. When HIGH, deselects the chip Input/Control BHE, BLE. BHE = LOW selects higher order byte WRITEs or READs on the SRAM BLE = LOW selects lower order byte WRITEs or READs on the SRAM Input/Control OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are Tri-stated, and act as input data pins Ground VSS. Ground for the device
41
12, 34 11, 33
Power Supply VCC. Power supply for the device
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CY62136V MoBL(R)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[5] ....................................-0.5V to VCC + 0.5V DC Input Voltage[5] .................................-0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................ 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Range Industrial Automotive Ambient Temperature [TA][7] -40C to +85C -40C to +125C VCC 2.7V to 3.6V
Electrical Characteristics Over the Operating Range
CY62136V-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled IOL = 2.1 mA Test Conditions IOH = -1.0 mA VCC = 2.7V VCC = 2.7V VCC = 3.6V VCC = 2.7V Industrial Automotive Industrial Automotive VCC = 3.6V, Industrial IOUT = 0 mA, Automotive CMOS Levels 7 1 20 2 100 -1 +1 2.2 -0.5 -1 2.4 0.4 VCC + 2.2 0.5V 0.8 +1 -0.5 -1 -10 -1 -10 7 7 1 CY62136V-70 2.4 0.4 VCC + 0.5V 0.8 +1 +10 +1 +10 15 20 2 100 V V V V A A A A mA mA mA A Min. Typ.[2] Max. Min. Typ.[2] Max. Unit
VCC Operating Supply f = fMax = 1/tRC, Current f = 1 MHz,
ISB1
Automatic CE CE > VCC-0.3V, Power-down Current-- VIN > VCC-0.3V or VIN < 0.3V, f = fMax CMOS Inputs Automatic CE CE > VCC-0.3V VCC = 3.6V Industrial Power-down Current-- VIN > VCC-0.3V or Automotive CMOS Inputs VIN < 0.3V, f = 0 1
ISB2
15
1 1
15 20
A
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 6 8 Unit pF pF
Thermal Resistance[6]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 2-layer printed circuit board FBGA 41.17 11.74 TSOPII 60 22 Unit C/W C/W
Notes: 5. VIL(min) = -2.0V for pulse durations less than 20 ns. 6. Tested initially and after any design or process changes that may affect these parameters. 7. TA is the "Instant-On" case temperature.
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CY62136V MoBL(R)
AC Test Loads and Waveforms
R1 VCC OUTPUT R1 VCC OUTPUT 30 pF R2 5 pF INCLUDING JIG AND SCOPE R2 ALL INPUT PULSES VCC Typ 10% GND Rise Time: 1 V/ns 90% 90% 10% Fall Time: 1 V/ns
INCLUDING JIG AND SCOPE
(c) (b)
Equivalent to: OUTPUT THEVENIN EQUIVALENT
RTH
(a)
V
Parameters R1 R2 RTH VTH
3.0V 1105 1550 645 1.75
Unit Ohms Ohms Ohms Volts
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC = 1.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, No input may exceed VCC + 0.3V 0 70 Conditions[9] Min. 1.0 0.5 Typ.[2] Max. 3.6 7.5 Unit V A
tCDR[6] tR[8]
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min.)
tCDR
VDR > 1.0 V
VCC(min.)
tR
CE
Notes: 8. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance.
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CY62136V MoBL(R)
Switching Characteristics Over the Operating Range [9]
55 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE Cycle[12, 13] Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[10, 11] 5 55 45 45 0 0 40 50 25 0 20 10 70 60 60 0 0 50 60 30 0 25 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[10] OE HIGH to High-Z[10, 11] 10 25 0 55 25 5 25 5 25 0 70 35 5 25 10 25 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. 70 ns Max. Unit
CE LOW to Low-Z[10] CE HIGH to High-Z[10, 11]
CE LOW to Power-up CE HIGH to Power-down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low-Z[10, 11]
BLE/BHE HIGH to High-Z[12]
WE HIGH to Low-Z[10]
Notes: 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 13. The minimum write cycle time for write cycle 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY62136V MoBL(R)
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[14, 15]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[15, 16]
ADDRESS
tRC CE tACE OE
tDOE
tPD tHZCE
tHZOE
BHE/BLE
ttLZOE LZOE
tHZBE
tDBE
tLZBE HIGH IMPEDANCE DATA OUT tLZCE tPU VCC SUPPLY CURRENT 50% 50% ISB ICC DATA VALID HIGH IMPEDANCE
Notes: 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW.
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CY62136V MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[12, 17, 18]
tWC ADDRESS
CE tAW WE tSA tPWE tHA
BHE/BLE
tBW
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Write Cycle No. 2 (CE Controlled)[12, 17, 18]
tWC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE
BHE/BLE
tBW
OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD
Notes: 17. Data I/O is high impedance if OE = VIH 18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 19. During this period, the I/Os are in output state and input signals should not be applied.
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CY62136V MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[13, 18]
tWC ADDRESS
CE tAW BHE/BLE tSA WE tSD DATA I/O NOTE 19 tHZWE DATA VALID IN tLZWE tHD tBW tHA
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19]
tWC ADDRESS
CE tAW tBW tSA WE tSD DATA I/O tHD tHA
BHE/BLE
NOTE 19
tHZWE
DATA VALID IN tLZWE
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CY62136V MoBL(R)
Typical DC and AC Characteristics
Normalized Operating Current vs. Supply Voltage Standby Current vs. Supply Voltage 35 MoBL 30 25 ISB (A) 20 15 10 5 0 2.2 2.7 3.2 SUPPLY VOLTAGE (V) 3.7 1.0 2.7 2.8 3.7 1.9 SUPPLY VOLTAGE (V)
1.4 1.2
MoBL 1.0 ICC 0.8 0.6 0.4 0.2 0.0 1.7
Access Time vs. Supply Voltage 80 70 60 50 TAA (ns) 40 30 20 10 1.0 1.9 2.7 2.8 3.7 MoBL
SUPPLY VOLTAGE (V)
Truth Table
CE H L L L L L L L L L L WE X H H H L L L H H H H OE X L L L X X X L H H H BHE X L H L L H L H L H L BLE X L L H L L H H L L H Inputs/Outputs High-Z Data Out (I/O0-I/O15) High Z (I/O8-I/O15); Data Out (I/O0-I/O7) Data Out (I/O8-I/O15); High Z (I/O0-I/O7) Data In (I/O0-I/O15) High Z (I/O8-I/O15); Data In (I/O0-I/O7) Data in (I/O8-I/O15); High Z (I/O0-I/O7) High-Z High-Z High-Z High-Z Mode Deselect/Power-down Read Read Read Write Write Write Deselect/Output Disabled Deselect/Output Disabled Deselect/Output Disabled Deselect/Output Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
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CY62136V MoBL(R)
Ordering Information
Speed (ns) 55 Ordering Code CY62136VLL-55BAI CY62136VLL-55ZI CY62136VLL-55ZXI 70 CY62136VLL-70BAI CY62136VLL-70ZI CY62136VLL-70ZXI CY62136VLL-70ZSE CY62136VLL-70ZSXE Package Diagram Package Type Operating Range Industrial
51-85096 48-ball Fine-Pitch Ball Grid Array (7 x 7 x 1.2 mm) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-free) 51-85096 48-ball Fine-Pitch Ball Grid Array (7 x 7 x 1.2 mm) 51-85087 44-pin TSOP II 44-pin TSOP II (Pb-free) 44-pin TSOP II 44-pin TSOP II (Pb-free)
Industrial
Automotive
Please contact your local Cypress sales representative for availability of these parts
Package Diagrams
48-ball FBGA (7 x 7 x 1.2 mm) (51-85096)
TOP VIEW
BOTTOM VIEW PIN 1 CORNER O0.05 M C O0.25 M C A B O0.300.05(48X)
PIN 1 CORNER (LASER MARK) 12 A B C 7.000.10 0.75 7.000.10 5.25 D E F G H 3 4 5 6
6
5
4
3
2
1 A B C D E
2.625
F G H
A
A
1.875 0.75
B
7.000.10 3.75 B 7.000.10
0.530.05
0.25 C
0.15(4X) 0.210.05 0.10 C
51-85096-*F
SEATING PLANE 0.36 C
1.20 MAX.
Document #: 38-05087 Rev. *D
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CY62136V MoBL(R)
Package Diagrams (continued)
44-pin TSOP II (51-85087)
51-85087-*A
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the products of their respective holders.
Document #: 38-05087 Rev. *D
Page 12 of 13
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY62136V MoBL(R)
Document History Page
Document Title: CY62136V MoBL(R) 2-Mbit (128K x 16) Static RAM Document Number: 38-05087 REV. ** *A ECN NO. 107347 116509 Issue Date 05/25/01 09/04/02 Orig. of Change SZV GBI Description of Change Changed from Spec #: 38-00728 to 38-05087 Added footnote 1 Added SL power bin Deleted fBGA package; replacement fBGA package available in CY62136CV30 Added Automotive Information for 70-ns Speed Bin. Added Footnotes # 3 and # 6. Corrected Typo in Electrical Characteristics for ICC(Max)-55 ns from 15 to 20 mA. Added SL row for ISB2 in the Electrical Characteristics table. Changed Package Name from Z44 to ZS44. Replaced `Z' with `ZS' in the Ordering Code. Added Lead-Free Package on page# 9 Changed Package Name from ZS44 to Z44 for the 44 TSOP II Package Replaced `ZS' with `Z' in the Ordering Code for Industrial Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court". Added FBGA Package for Industrial Operating range. Removed SL Power bin. Updated Ordering Information table.
*B
269729
See ECN
SYT
*C
344595
See ECN
SYT
*D
486789
See ECN
VKN
Document #: 38-05087 Rev. *D
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